1. Field
Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device with a recess gate and a method for fabricating the same.
2. Description of the Related Art
With high integration of semiconductor devices, the gate length of a transistor has continuously decreased. Accordingly, drain induced barrier lowering (DIBL), threshold voltage (Vt) roll-off or the like occurs due to a short channel effect.
Therefore, a method for increasing a channel length by applying a recess gate to a cell transistor has been recently adopted. Furthermore, an important circuit such as a sense amplifier, in which the characteristic of a transistor determines the device characteristic, in a peripheral circuit region employs a recess gate, like a cell transistor.
FIG. 1A is a cross-sectional view of a conventional semiconductor device with a recess gate.
Referring to FIG. 1A, an isolation region 12 is formed in a substrate 11, and a trench 13 is formed in an active region of the substrate 11. A gate dielectric layer 14 is formed on the surface of the trench 13. A silicon-containing electrode 15 is formed over the gate dielectric layer 14 so as to gap-fill the trench 13. The top surface of the silicon-containing electrode 15 has a higher level than the top surface of the substrate 11. A metal-containing electrode 16 is formed over the silicon-containing electrode 15. A gate hard mask layer 17 is formed over the metal-containing electrode 16. Accordingly, a recess gate structure including the silicon-containing electrode 15, the metal-containing electrode 16, and the gate hard mask layer 17 is formed. Source/drain regions 18 (not illustrated) are formed in the substrate 11 at both sides of the recess gate structure. Accordingly, a recess channel of which the channel length is increased by the silicon-containing electrode 15 is formed.
In FIG. 1A, the silicon-containing electrode 15 includes polysilicon, and is doped with a dopant to have conductivity. For example, undoped polysilicon is deposited to gap-fill the trench 13, and a dopant is then implanted. The dopant may include an N-type dopant or P-type dopant depending on the type of the transistor.
FIG. 1B is a diagram illustrating a conventional impurity doping method for a silicon-containing electrode.
Referring to FIG. 1B, when an implant method is used to implant a dopant, ‘Rp’ may be set at a deep position of the trench 13 as indicated by reference numeral {circle around (1)}.
In the conventional impurity doping method, however, regions where Rp is set at a relatively shallow position and source/drain regions are to be formed may be damaged as indicated by reference numerals {circle around (2)} and {circle around (3)}.
Furthermore, when a planar gate structure and a recess gate structure are formed at the same time, it may be difficult to implement a dopant implant process that satisfies both of the planar gate structure and the recess gate structure.